Manatee: A Multicore Interference Analysis Tool for Embedded SoC Evaluation

Axel Wiedemann1, Florian Haas1 and Sebastian Altmeyer1

  1. Faculty of Applied Computer Science, University of Augsburg
    Universitätsstr. 6a, 86159 Augsburg, Germany
    {wiedemann,-,altmeyer}@es-augsburg.de

Abstract

Interferences on shared resources are the main factor limiting the employment of multicore architectures in many embedded use cases. Research on these interferences and enhancements, for example in memory hierarchies, could alleviate this restriction. This however requires more awareness of contention for shared resources during the design and development process of System on Chips (SoCs). As an answer we present the concept of a tool which brings this awareness to the RISC-V hardware development framework Chipyard. It extends Chipyard's agile development focus by adding the capabilities for quick feedback on changes regarding shared resource contention. A partial realisation further allows first tests and evaluation on use case basis.

Key words

parallel real-time system, memory hierarchy, FPGA prototyping frame-work

Digital Object Identifier (DOI)

https://doi.org/10.2298/CSIS240724024W

Publication information

Volume 22, Issue 2 (April 2025)
Special Issue on Computer Systems and Resource Awareness
Year of Publication: 2025
ISSN: 2406-1018 (Online)
Publisher: ComSIS Consortium

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How to cite

Wiedemann, A., Haas, F., Altmeyer, S.: Manatee: A Multicore Interference Analysis Tool for Embedded SoC Evaluation. Computer Science and Information Systems, Vol. 22, No. 2, 591-621. (2025), https://doi.org/10.2298/CSIS240724024W