UDC 004.31.26, DOI: 10.2298/CSIS1001189W

The Design and Evaluation of Hierarchical Multi-level Parallelisms for H.264 Encoder on Multi-core Architecture

Haitao Wei1, Junqing Yu1 and Jiang Li1

  1. School of Computer Science & Technology, Huazhong University of Science & Technology
    430074 Wuhan, China
    yjqing@hust.edu.cn

Abstract

As a video coding standard, H.264 achieves high compress rate while keeping good fidelity. But it requires more intensive computation than before to get such high coding performance. A Hierarchical Multi-level Parallelisms (HMLP) framework for H.264 encoder is proposed which integrates four level parallelisms � frame-level, slice-level, macroblock-level and data-level into one implementation. Each level parallelism is designed in a hierarchical parallel framework and mapped onto the multi-cores and SIMD units on multi-core architecture. According to the analysis of coding performance on each level parallelism, we propose a method to combine different parallel levels to attain a good compromise between high speedup and low bit-rate. The experimental results show that for CIF format video, our method achieves the speedup of 33.57x-42.3x with 1.04x-1.08x bit-rate increasing on 8-core Intel Xeon processor with SIMD Technology.

Key words

H.264 encoder; Hierarchical Multi-level Parallelisms; Multi-core Architecture

Digital Object Identifier (DOI)

https://doi.org/10.2298/CSIS1001189W

Publication information

Volume 7, Issue 1 (February 2010)
Advances in Computer Animation and Digital Entertainment
Year of Publication: 2010
ISSN: 1820-0214 (Print) 2406-1018 (Online)
Publisher: ComSIS Consortium

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How to cite

Wei, H., Yu, J., Li, J.: The Design and Evaluation of Hierarchical Multi-level Parallelisms for H.264 Encoder on Multi-core Architecture. Computer Science and Information Systems, Vol. 7, No. 1. (2010)